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Design Verification Internship

The Programme

Internship period: 6 months - estimated starting date is 1 June 2018

  • Receive training on ASIC design and verification flow, Storage System-on-chip Architecture, SystemVerilog language and UVM methodology, EDA tool usage, Defining and building complex verification environment
  • Involve to work for real projects including building and developing verification environment, verifying functionality of our current development Storage System-on-chip ASIC
  • Have monthly salary of 7,000,000 VND
  • Have company paid of Social Insurance and Medical Insurance
  • Receive daily lunch allowance of 30,000 VND
  • Full-time contract with competitive salary and benefit package will be offered to the right candidates who can demonstrate their technical ability, potential motivation and achieved good performance during internship upon completion of the internship program

Required Skills and Abilities

  • Final year student who has completed the final year thesis in the current year or fresh graduate in Computer Science Engineering, Electric-Electrical Engineering
  • Minimum GPA 7.5/10 with the high score on Digital Logic Design, Microcontroller, Computer
  • Architecture, Object Oriented Programming courses is a plus
  • Good English skills in reading, writing and speaking is a plus
  • Use of a UNIX environment and shell programming is a plus
  • Hands-on projects using VHDL/Verilog is a plus
  • Candidate must be available for full time employment during the internship period.

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